The basis of the microcontroller (see Fig. 1) is an 8-bit Arithmetic Logic Unit (ALU). The memory of the MK has a Harvard architecture, i.e. logically divided: into program memory - PP (internal or external), addressed by a 16-bit command counter (SC) and data memory - internal (Resident data memory - RPD) 128 (or 256) bytes, as well as external (External data memory – VPD) up to 64 KB. Physically, program memory is implemented on ROM (read only), and data memory is implemented on RAM (data can be written and read).

Reception and delivery of external signals is carried out through 4 eight-bit ports Р0..Р3. When accessing external program memory (EPM) or data memory (VPD), ports P0 and P2 are used as a multiplexed external Address/Data bus. P3 port lines can also perform alternative functions (see Table 1).

The 16-bit DPTR register forms the VPD address or Program Memory base address in the Accumulator conversion instruction. The DPTR register can also be used as two independent 8-bit registers (DPL and DPH) to store operands.

8-bit internal command register (RK) receives the code of the command being executed; this code is decoded by the control circuit, which generates control signals (see Fig. 1).

Access to special function registers - RSF (SFR - in Fig. 1 they are circled with a dotted line) is possible only using direct byte addressing in the address range from 128 (80h) and more.

Resident data memory (RDD) in the first models of microcontrollers of the MCS-51 family had a capacity of 128 bytes. The lower 32 bytes of the RPD are also general-purpose registers - RON (4 banks of 8 RONs each). The program can apply to one of the 8 RONs of the active bank. The selection of the active bank of RONs is carried out by programming two bits in the processor status register - PSW.

Table 1 - MCS-51 pin assignment

Pin No.	Designation	Purpose
1..8	P1	8-bit quasi-bidirectional I/O port
9	RST	Reset signal (active level - high); The RST signal resets: the PC and most Special Function Registers (SFRs), disabling all interrupts and timers; selects RON Bank 0; writes "all ones" to ports P0_P3, preparing them for input; writes code 07H to the stack pointer (SP);
10..17		8-bit quasi-bidirectional I/O port; after writing to the corresponding bit "1" - performs additional (alternative) functions: Serial port input - RxD; Serial port output - TxD; External interrupt input 0 - ~INT0; External interrupt input 1 - ~INT1; Timer/counter input 0 - T0; Timer/counter input 1 - T1; Strobe output. signal when writing to the VPD - ~ WR; Strobe output. signal when reading from the VPD - ~ RD;
18, 19	X1, X2	Conclusions for connecting a quartz resonator or LC circuit;
20	GND	General conclusion;
21..28	P2	8-bit quasi-bidirectional I/O port; or output address A in external memory mode (VPP or VPD);
29	PME	External Program Memory read strobe, issued only when accessing external ROM;
30	ALE	External memory address strobe (VPP or VPD);
31	EA	Disabling the RPP, the level "0" at this input switches the MK to a selection of commands only from the runway ;
39..32	P0	8-bit bidirectional I/O port; when accessing External Memory, it issues addresses A (which are written to an external register by the ALE signal), and then exchanges a byte synchronously with the signal ~PME (for commands) or ~WR,~RD (for data in VPD), when accessing External Memory all units are written to the port register P0, destroying the information stored there;
40	Ucc	Supply voltage output

Switching banks of RONs simplifies the execution of subroutines and handling of interrupts, because. it is not necessary to transfer the contents of the RONs of the main program to the stack when calling the subroutine (it is enough to go to another active RON bank in the subroutine).

Access to the RPD is possible using indirect or direct byte addressing (direct byte addressing allows accessing only the first 128 bytes of the RPD).

The extended RPD area (for microcontrollers of the MCS-52 family and subsequent families) from address 128 (80h) to 255 (FFh) can only be addressed using the indirect addressing method.

Table 2 - Block Registers of Special Functions (s f r)

	Mnemo code	Name
0E0h	*ACC	Battery
0F0h	*B	Register battery expander
0D0h	*PSW	Processor Status Word
0B0h	* P3	Port 3
0A0h	* P2	Port 2
90h	* P1	Port 1
80h	*P0	Port 0
0B8h	* IP	Interrupt Priority Register
0A8h	*IE	Interrupt mask register
99h	SBUF	Serial transceiver buffer
98h	* SCON	Serial Port Control/Status Register
89h	TMOD	Timer/Counter Mode Register
88h	* TCON	Timer/Counter Control/Status Register
8Dh	TH1	Timer 1 (high byte)
8bh	TL1	Timer 1 (low byte)
8ch	TH0	Timer 0 (high byte)
8ah	TL0	Timer 0 (low byte)
83h	DPH	Data Pointer Register (DPTR) (high byte)
82h	DPL	Data Pointer Register (DPTR) (low byte)
81h	SP	Stack pointer register
87h	PCON	Demand power control register

2. SOFTWARE MODEL MCS–51

COMMAND TYPES MCS–51

Almost half of the commands are executed in 1 machine cycle (MC). With a crystal oscillator frequency of 12 MHz, the execution time for such a command is 1 μs. The remaining commands are executed in 2 machine cycles, i.e. for 2 ms. Only multiplication (MUL) and division (DIV) instructions are executed in 4 machine cycles.

During one machine cycle, there are two accesses to the Program Memory (internal or external) to read two bytes of the instruction, or one access to the External Data Memory (EDM).

3. METHODS (METHODS) OF ADDRESSING MCS–51

1. REGISTER ADDRESSING - 8-bit operand is located in the RON of the selected (active) bank of registers;

2 DIRECT ADDRESSING (indicated by the sign - #) - the operand is located in the second (and for a 16-bit operand and in the third) byte of the command;

3 INDIRECT ADDRESSING (indicated by the - @ sign) - the operand is located in the Data Memory (RPD or VPD), and the address of the memory cell is contained in one of the RONs of indirect addressing (R0 or R1); in the PUSH and POP commands, the address is contained in the stack pointer SP; the DPTR register can contain a VPD address up to 64K;

4 DIRECT BYTE ADDRESSING – (dir) – used to access RPD cells (addresses 00h…7Fh) and special function registers SFR (addresses 80h…0FFh);

5 DIRECT BIT ADDRESSING - (bit) - is used to access separately addressable 128 bits located in RPD cells at addresses 20H ... 2FH and to separately addressable bits of special function registers (see Table 3 and program model);

6 INDIRECT INDEX ADDRESSING (denoted by the @ sign) - simplifies viewing tables in the Program Memory, the PP address is determined by the sum of the base register (PC or DPTR) and the index register (Battery);

7 IMPLICIT (BUILT-IN) ADDRESSING - the instruction code contains an implicit (by default) reference to one of the operands (most often to the Accumulator).

4. PROCESSOR STATUS WORD (PSW) FORMAT

C - Carry (CARY) or borrow flag, also functions as a "boolean accumulator" in bit-operated instructions;

AC – auxiliary (additional) carry flag – set to "1" if the addition command (ADD, ADDC) had a carry from the low order tetrad to the high order (i.e. from the 3rd bit to the 4th bit);

F0 - user flag - set, reset and checked by software;

RS1	RS0	Bank	Address (dir)
0	0	0	00h..07h
0	1	1	08h..0Fh
1	0	2	10h..17h
1	1	3	18h..1Fh

RS1,RS0 – Register bank selection:

OV - Arithmetic overflow flag; its value is determined by the XOR operation of the input and output carry signals of the most significant bit of the ALU; a single value of this flag indicates that the result of an arithmetic operation in the two's complement code is out of range: –128…+127; when performing the division operation, the OV flag is reset, and in the case of division by zero, it is set; when multiplying, the OV flag is set if the result is greater than 255 (0FFH);

Bit PSW - Reserved, contains a trigger, available for writing or reading;

P - parity flag - is the addition of the number of single bits in the accumulator to an even number; is formed by a combinational circuit (programmatically available only for reading).

The MCS-51 microcontrollers do not have the "Z" flag. But in the conditional jump instructions (JZ, JNZ), the combinational circuit checks the current (zero or non-zero) contents of the Accumulator.

All commands of transfers and exchange of operands can be carried out through the Accumulator (see Fig. 3). Moreover, transfers from / to External Memory (Program Memory or Data Memory) can only be carried out through the Battery.

Most transfers can also be made via a forward byte (dir). There are even dir-to-dir transfers (see Figure 3).

Missing transfers from RON to RON can be implemented as transfers from RON to the forward byte dir (given that the RONs are located in the initial area of ​​the Resident Data Memory, the cells of which can be addressed as dir).

XCH exchange commands allow you to send bytes without destroying both operands.

Arithmetic commands are executed only in the Accumulator. Therefore, the first operand must first be placed in the Accumulator and then add or subtract the second operand. The result is placed in the Accumulator.

The SUBB subtraction command is executed only with a borrow (i.e., the Cary flag is also subtracted from the result). Therefore, in order to execute a subtraction instruction without borrowing, it is necessary to first execute the Clear Flag C (CLRC) instruction.

The instruction for multiplying one-byte operands - MULAB - places a two-byte (16 bit) result: the low byte is in the Accumulator, the high byte is in register B.

The result of executing the instruction for dividing one-byte operands - DIVAB - is placed: the quotient - a Accumulator, the remainder - in register B.

The INC arithmetic instruction adds one to the selected operand. The DEC arithmetic instruction subtracts one from the selected operand. The Accumulator Decimal Correction (DAA) instruction helps you add binary coded decimal (BCD) numbers without converting them to hexadecimal (hex) format. Source operands must be in BCD format, i.e. in each tetrad of one byte there are only numbers from 0 to 9 (there cannot be hexadecimal numbers: A, B, C, D, E, F). Therefore, one byte can contain numbers from 00 to 99 for packed BCD numbers, or numbers from 0 to 9 for unpacked BCD numbers.

The DA A - decimal correction command performs actions on the contents of the Accumulator after adding the BCD numbers in the processor (the numbers were added according to the laws of hexadecimal arithmetic) as follows (see example):

· if the contents of the low-order tetrad of the Accumulator is greater than 9 or the auxiliary carry flag is set (AC = 1), then 6 is added to the contents of the Accumulator (that is, the missing six digits in hex format);

· if after that the content of the high order of the Accumulator is greater than 9 or the flag C is set, then the number 6 is added to the high order of the Accumulator.

The decimal correction instruction DA A is not used after the increment instruction (INC) because the increment instruction does not affect (change) the C and AC flags.

Logic commands:

Logical "AND" - ANL,

Logical "OR" - ORL,

The XOR logical command - XRL - is executed in the Accumulator (as well as arithmetic), but it is possible to execute logical commands also in the direct address byte (dir). In this case, the second operand can be:

in the battery or

An immediate operand in an instruction.

Rotation instructions (RR A, RL A) and rotation instructions through the CARY flag (RRC A, RLC A) rotate the contents of the Accumulator by 1 bit. Bit operands are sent only through the C flag.

The architecture of the MCS-51 family is largely predetermined by its purpose - building compact and cheap digital devices. All functions of the microcomputer are implemented using a single microcircuit. The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. Microcontrollers of the MCS-51 family allow you to perform both the tasks of controlling various devices and implementing individual nodes of the analog circuit. All microcircuits of this family work with the same command system MCS-51, most of them are performed in the same cases with matching pinout(numbering of legs for the case). This allows you to use chips from different companies for the developed device - Maxim, Atmel, NXP, etc. (catalog..php?page=components_list&id=39"> s.m. Search by parameters) without altering the circuit diagram of the device and program.

Figure 1. Block diagram of the I8751 controller

The block diagram of the controller is shown in Figure 1 and consists of the following main functional units: a control unit, an arithmetic logic unit, a timer/counter unit, a serial interface and interrupt unit, a program counter, data memory, and program memory. Bilateral exchange is carried out using an internal 8-bit data highway.

Let's take a closer look at the purpose of each block. Almost all representatives of the MCS-51 family are built according to this scheme.. Various microcircuits of this family differ only in special-purpose registers (including the number of ports). Command system of all controllers of the MCS-51 family contains 111 basic commands with a format of 1, 2 or 3 bytes and does not change when moving from one chip to another. This provides excellent portability of programs from one chip to another.

Control and synchronization unit

The control and synchronization unit (Timing and Control) is designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:

• - device for forming time intervals,
• - I/O logic,
• - instruction register,
• - electricity consumption management register,
• - command decoder, computer control logic.

Time slotting device is intended for generation and output of internal synchronization signals of phases, cycles and cycles. The number of machine cycles determines the duration of instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for the multiplication and division instructions, the duration of which is four machine cycles. Let us denote the frequency of the master oscillator through F g. Then the duration of the machine cycle is 12/F g, or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that ensure the exchange of information with external devices through the input/output ports P0-P3.

Command register is designed to record and store an 8-bit operation code of the command being executed. The operation code, with the help of a command decoder and computer control logic, is converted into a microprogram for command execution.

Demand Control Register (PCON) allows you to stop the operation of the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by toggling bits in the PCON demand control register. For the nMOS manufacturing option (1816 series or foreign chips that do not have the letter "c" in the middle of the name), the power control register PCON contains only one bit that controls the baud rate of the SMOD serial port, and there are no power consumption control bits.

Arithmetic Logic Unit (ALU) is a parallel eight-bit device that provides arithmetic and logical operations. ALU consists of:

• - accumulator registers, temporary storage registers TMP1 and TMP2,
• - ROM constants,
• - adder,
• - additional register (register B),
• - accumulator (ACC),
• - program status register (PSW).

Register battery and holding registers- eight-bit registers designed to receive and store operands for the duration of operations on them. These registers are not programmatically accessible.

ROM constants ensures the development of a correcting code for binary-decimal data representation, a mask code for bit operations, and a constant code.

Parallel 8-bit adder is a combinational circuit with sequential transfer, designed to perform arithmetic operations of addition, subtraction and logical operations of addition, multiplication, disparity and identity.

Register B- an eight-bit register used during multiplication and division operations. For other instructions, it can be considered as an additional scratchpad register.

Battery- an eight-bit register designed to receive and store the result obtained when performing arithmetic-logical operations or shift operations

Serial Interface and Interrupt Block (SIP) is designed to organize the input-output of sequential information flows and organize the program interrupt system. The block includes:

1. - PIP buffer,
2. - control logic,
3. - control register,
4. - transmitter buffer,
5. - receiver buffer,
6. - serial port transceiver,
7. - interrupt priority register,
8. - interrupt enable register,
9. - logic for processing interrupt flags and a vector generation scheme.

Program Counter is designed to form the current 16-bit address of the internal program memory and the 8/16-bit address of the external program memory. The program counter consists of a 16-bit PC buffer, a PC register, and an increment circuit (incrementing content by 1).

Data memory (RAM) is intended for temporary storage of information used during the execution of the program.

Ports P0, P1, P2, P3 are quasi-bidirectional input-output ports and are designed to ensure the exchange of information between the OEVM and external devices, forming 32 input-output lines.

Timer device The basic models of the family have two programmable 16-bit timer/counters (T/C0 and T/C1) that can be used both as timers and as external event counters.

Program Status Register (PSW) is designed to store information about the state of the ALU during the execution of the program.

Program memory (EPROM) designed to store programs and is a read-only memory (ROM). Various microcircuits use masked ROMs that are erased by ultraviolet radiation or FLASH ROM.

Data Pointer Register (DPTR) is designed to store the 16-bit address of external data memory or program memory.

Stack pointer (SP) is an eight-bit register designed to organize a special data memory area (stack) in which any memory cell can be temporarily stored.

The state of the interrupt system is polled at the end of each machine cycle in phase S5P2, with the exception of RETI instructions and any instructions that access the IE and IP registers. It takes 38 to 86 periods of frequency fOSC from the moment the interrupt request is committed to servicing the interrupt, depending on the phase of the request and the number of machine cycles of the instruction during which the request was received.

When the interrupt is implemented in hardware, the LCALL addr16 instruction is executed, which ensures that the current state of the program counter is stored on the stack (remembering the return address), and jumping to the start address addr16 of the corresponding service procedure. Each interrupt request source has its own associated

start address (interrupt vector):
			External interrupt INT0.
			Timer/counter interrupt TC0.
			External interrupt INT1.
			Timer/counter interrupt TC1.
			Serial port interrupt.

2.7. Addressing methods and command system of the MCS-51 family

The command system of the MCS-51 family is focused on organizing flexible data input/output through universal ports P0...P3 and primary information processing. Particular attention is paid to operations with bits and transfer of control by their value. The instructions that perform such operations form a large group and, together with the corresponding hardware, form the so-called "Boolean processor" as part of the MCS-51 architecture.

The command system provides the programmer with the ability to use most of the operations with a full set of addressing methods and software-accessible hardware resources.

2.7.1. Addressing methods

Each instruction tells the processor the operation to be performed and the methods to access the operands. The command code has several fields that have a specific functional purpose. The most important fields of any command are the operation code (COP), which determines the action of the command, and the address part. The fields of the address part contain information about the addresses of the operands and the result of the operation, and in some cases, information about the address of the next instruction.

If the address points to the number of the memory cell in which the operand is located or where it is entered, then it is called a direct address.

Addressing methods are a set of mechanisms for accessing operands. Some of them are simple, resulting in a compact instruction format and fast access to the operand, but have a limited amount of available resources. Others allow you to operate with all the resources available in the system, but the command turns out to be long,

input and execution is spent a lot of time. The set of addressing methods in each instruction set is a compromise combination of known addressing mechanisms chosen by architecture designers based on the set of tasks to be solved.

The following are the main addressing methods used in the MCS-51 Family Command System.

Implicit addressing. The command does not contain explicit indications about the address of the operand participating in the operation or the address at which the result of the operation is placed, but this address is implied. In commands, the accumulator is most often implicitly addressed as the destination of the result of an operation. For example, the result of adding the contents of the accumulator (A) and the R1 register of the current databank by the ADD A,R1 instruction is written to the implicitly addressed accumulator. The entire specified instruction occupies one byte in memory, while the address of only the accumulator (8Eh of the SFR area) contains one byte.

Direct Addressing. In the address field of the command, contain

It is not the address of the operand that lives, but the operand itself. Direct addressing is indicated by the special character # before the number. For example, the command MOV A,#15h loads the hexadecimal number 15 (the second byte of the command) into the accumulator. In the command system, direct addressing is denoted as #data, where data is a number

(data = 00h...FFh).

Direct Addressing. The instruction address field specifies the direct address of the data memory location in which the operand is located or where it is written. For example, the MOV A,15h instruction loads the contents of the DSEG cell at address 15h into the accumulator. The memory cell is directly addressable, while the accumulator is implicitly addressed. Depending on the location of the addressed operand, direct addressing is subdivided into register direct addressing and absolute addressing.

Direct register addressing. The command address field contains the direct register address of the current register bank. There are eight registers in each bank, and a three-bit direct address is required to address them. In the command mnemonics, the addressable register is denoted by Rn, where n=0...7. All fields of the command fit in one byte. Such addressing is called short. For example, MOV R4,R1.

Direct absolute addressing allows you to access any DSEG cell and SFR area. The direct address in this case takes one byte, and the command takes two bytes. In the command system, the direct address byte is denoted by the word direct (direct) (direct = 00h ... FFh). For example, the instruction MOV 80h,R2 (or MOV P0,R2) loads the contents of register R2 of the current databank into port P0 (location 80h of the SFR). If both operands are direct absolute addressable, then the instruction becomes a three-byte instruction (eg MOV 80h,15h).

indirect addressing. The address field contains the address of the memory location where the direct address of the operand is located. In the command system, indirect addressing is indicated by the @ special character. property

registers R0 and R1 (@Ri, i = 0.1) of each register bank have to store the direct address. For example, if the contents of the R1 register of the current register bank is 15h, then the MOV A,@R1 instruction will perform the same action as the MOV A,15h instruction above - it will load the contents of the DSEG memory location with address 15h into the accumulator. However, the MOV A, @ R1 command is one-byte, but most importantly, it is possible to programmatically change the address by changing the contents of the R1 register.

Relative addressing. With relative addressing, the direct address is formed by adding the base address to the address field of the command. The contents of the program counter are used as the base address, and the instruction's address field is an eight-bit rel (relative) offset. The rel number is interpreted by the command as a signed integer represented in two's complement. Its presentation range is (-128...+127). When determining the rel number, keep in mind that the program counter points to the next instruction to be executed. Relative addressing is widely used in control transfer commands, which allows the creation of relocatable program modules. Control transfer commands with relative addressing allow branching relative to the current position of the PC program counter in both directions by (-128...+127) bytes.

In assembly language programs, the offset field can be used to specify the label to jump to. As a result of the translation, the assembler will calculate the offset value if it does not exceed (-128…+127). Otherwise, an error message will be issued.

Basic addressing represents a kind of relative addressing. The direct address in this case is formed by adding the address specified in the command to the contents of the base register, which stores the base address. The function of the base register in the MCS-51 family is performed by the DPTR data pointer register or the PC program counter. This type of addressing is especially useful when processing tables and data arrays. In the MOVC A,@A+DPTR and MOVC A,@A+PC instructions, the 16-bit direct address is formed as the sum of the contents of the DPTR and A or PC and A registers.

Page Addressing. When using page addressing, memory is divided into a number of pages of the same length. Page addressing is carried out by a separate page register, and memory cells within a page are addressed by the address contained in the instruction. The direct address is formed by concatenating (attaching) the address of the pages and the address of the memory cell within the page. In the MOVX A,@Ri instruction, port P2 (high byte of the address) performs the function of the page register, and the content of the register Ri (low byte of the address) specifies the address within the page. In this case, the memory is divided into 256 pages of 256 cells in each of them.

Stack Addressing used in addressless commands and is a combination of auto-increment and auto-decrement addressing methods, working on the principle of LIFO (L ast I nput - F irst O utput) - “last in - first out”. The stack is located in DSEG and grows in the direction of increasing address. The address of the top of the stack is contained in the stack pointer SP. When a byte is pushed onto the stack, the contents of SP are incremented first, and then the address is written to. When reading a byte from the stack, first read at the address pointed to by SP, and then decrement SP. When using a stack, keep in mind that the stack depth (the maximum number of memory cells occupied by the stack) is not controlled by the hardware. With an excessive increase in the stack, memory cells not intended for it can be occupied with the loss of information in them. The hardware stack is used to store the return address when servicing an interrupt.

2.7.2. MCS-51 Family Command System

The command system is presented in tables A2.1...A2.6 of Appendix 2. The tables indicate the name of the command, its mnemonic, binary operation code, the effect of the executed command on the flags C, OV, AC and P, the length of the command in bytes (B) and execution time in machine cycles (C), as well as the content of the conversion performed by the instruction. A comma is used as a separator for address fields in commands. To improve readability, spaces can be added after the comma if supported by the assembler being used.

The whole set of commands can be divided into 5 groups: data transfer operations, arithmetic operations, logical operations, operations with bits and control transfer operations.

Data transfer operation command group(Table A2.1) co-

holds MOV commands (data transfer between DSEG and RSEG), MOVC (between CSEG and A), MOVX (between XSEG and A), PUSH and POP stack access commands, and two XCH and XCHD exchange commands. All data transfer instructions whose destination is the accumulator set the parity flag P of the contents of the accumulator, and direct addressing instructions whose destination is the PSW register change all flags. The most capacious is the MOV instruction, which uses four addressing methods: direct register (A, Rn, DPTR), direct (direct), indirect (@Ri), direct (#data, #data16). The second operand of the command is the source, the first operand is the destination. There are three addressing methods (except direct) for specifying the destination, and all four for specifying the source. The three-byte MOV direct,direct instruction provides a transfer between any two memory cells (DSEG and SFR), including RSEG. For exchange with RSEG, special two- and one-byte formats are provided:

The special instruction MOV DPTR,#data16 loads a 16-bit DPTR pointer with the value data16.

The MOVC instruction allows you to read information from the CSEG program memory not into the command register of the control device, but into the accumulator of the operating device. The command uses two addressing methods: based on DPTR and relative to PC. In both cases, the unsigned integer offset (index) is stored in the accumulator. The accumulator also serves as the receiver of the result. The command allows you to perform quick recoding by tables.

External memory is accessed using the MOVX instruction. The exchange is performed by bytes between the accumulator and the external XSEG. An XSEG cell can be addressed in two ways: indirectly through a 16-bit pointer DPTR and page-wise indirectly through an 8-bit pointer Ri, i=0,1. In the latter case, the page register is P2.

Unaddressed PUSH and POP commands provide data transfer

between DSEG, RSEG and SFR.

The XCH exchange command provides a two-way byte exchange, and the XCHD command provides the lower tetrads of byte operands.

Group of instructions for arithmetic operations(Table A2.2) co-

holds Add ADD, Carry Add ADDC, Borrow Subtract SUBB, Increment and Decrement by One INC and DEC, Packed BCD Decimal Correction, Multiply MUL, and Divide DIV. Operations are performed on unsigned integers. In the operations of addition and subtraction, the accumulator is the first operand and the destination of the result. Direct register, direct absolute, direct and indirect addressing are used to define the second operand. The INC and DEC operations apply to an accumulator, a directly addressable register, a directly or indirectly addressable memory location. In addition, the INC operation applies to the contents of the 16-bit DPTR pointer register.

Integer multiplication and unsigned division operations involve the accumulator and register B. Multiplication multiplies the 8-bit value of A by the 8-bit value of B, and writes the 16-bit result to pair BA. In this case, register B stores the highest part of the product. The OV flag is set if the product is greater than 255. When an 8-bit value A is divided by an 8-bit value B, the quotient is written to A and the remainder to B. An attempt to divide by 0 sets the OV overflow flag.

The accumulator decimal correction command DA is placed after the addition command. The terms must be represented in BCD code. Correction is performed in a standard way.

Logic instruction group(Table A2.3 ) contains three typical operations: ANL - logical AND, ORL - logical OR, XRL - logical exclusive OR. Source of first operand

is either the accumulator A or a directly addressable memory cell. The second operand is specified by one of the four basic addressing methods. The group also includes single operations above the contents of the accumulator: CLR - clears, CPL - inversions, as well as RL, RLC, RR and RRC - operations of cyclic and extended shifts to the right and left. This also includes the operation of exchanging tetrads in the SWAP accumulator, which can be interpreted as a cyclic shift of a byte by four bits.

Bit operation instruction group(table A2.6) contains co-

commands SETB - set a bit to 1, CLR - reset a bit to 0, CPL - bit inversion, ANL and ORL - logical AND and logical OR of the contents of the flag C and a directly addressed bit, MOV - bit forwarding.

V In bitwise operations, the C flag plays the role of a Boolean accumulator. The contents of the C flag or the directly addressable bit of the BSEG area are used as operands. In ANL and ORL operations, you can use the content of the directly addressed bit (bit) or the inverse of the content (/bit).

V this group also includes conditional jump instructions with relative 8-bit offset rel. A conditional branch can be executed either when the bit is set (JB command) or cleared (JNB command). Of particular note is the JBC instruction, which, when a bit is set, implements a branch and at the same time resets the bit to 0.

Control Transfer Command Group(Tables A2.4 and A2.5)

holds jump unconditional instructions AJMP, LJMP, SJMP, JMP, jump conditional JZ, JNZ, CJNE, call ACALL, LCALL, return RET, RETI, and update with conditional jump DJNZ. The empty NOP command is also included here.

V Relative addressing is widely used in control transfer commands to allow the creation of relocatable program modules. The relative address is 8-bit offset rel is a signed byte that provides a transition to (-128… +127) bytes relative to the current position of the PC. Either the direct addr16 or the indirect @A+DPTR address can be used to jump to any other point in the 64 KB address space. In the latter case, the content of A is interpreted as an unsigned integer. A variant of short direct addressing addr11 within the 2K current page is introduced for compatibility with the MCS-48 family.

All of these types of addressing are used in jump instructions. Call commands use only direct addr16 and in-page addr11 addressing methods. All conditional commands use only relative addressing.

When the microcontroller recognizes an interrupt request, it issues an LCALL addr16 instruction, which automatically stores the return address on the stack. Program state information (the contents of the PSW register) is not automatically saved. Wherein

UDC 681.5, 681.325.5 (075.8)

BBK 32.973.202-018.2 i 73

Shcherbina A. N.Computing machines, systems and networks. Microcontrollers and microprocessors in control systems: Cheb. allowance / A.N. Shcherbina, P.A. Nechaev-SPb.: From the Polytechnic. un-ta, 2012.-226 p.

Corresponds to the content of the state educational standard for areas of training and specialties in the field of management in technical systems, electric power and electrical engineering and the content of the exemplary curriculum of the discipline "Computers, systems and networks".

The fundamental questions of the logical organization of microprocessor systems are considered on the example of the basic architecture of the MCS-51 microcontroller family from Intel. The technology of programming microcontrollers in Assembler and SI languages ​​is described.

It can be useful for students and teachers of higher technical institutions, specialists in automation of technological processes and production equipment, as well as for design engineers of microprocessor systems.

It also corresponds to the content of the state educational standard of the disciplines "Microcontrollers and microprocessors in control systems" and "Electronic devices of automation" for bachelor's, engineering and master's training in the direction 140400 "Electric power and electrical engineering".

Published by decision of the editorial and publishing council

St. Petersburg State Polytechnic University.

© Shcherbina A. N., Nechaev P. A., 2012

© St. Petersburg State

polytechnic university, 2012

ISBN 978-5-7422-3553-8

Introduction.. 7

Chapter 1. Architecture of the MCS51 family. 10

1.1 General characteristics 10

1.2 Block diagram 11

1.3 8051 microcontroller pin assignment 15

1.4 Memory organization 17

1.4.1 Program memory (ROM) 18

1.4.2 Data memory (RAM) 19

1.4.3 Registers of special functions. twenty

1.4.4 Flag Register (PSW) 23

1.5 Control and synchronization device 26

1.6 Organizing I/O ports 27

1.6.1 General information. 27

1.6.2 Alternative functions. 27

1.7. Timers / counters of microcontrollers of the 8051 family. 28

1.7.1. Structure of timers-counters. 28

1.7.2 Operating modes of timers-counters. thirty

1.8. Serial port 32

1.8.1. The structure of the serial port. 32

1.8.2. Transceiver control/status register SCON.. 34

1.8.3. Power control register PCON.. 36

1.9. Interrupt System 37

1.9.1. The structure of the interrupt system. 37

1.9.2 Execution of the interrupt routine. 40

Chapter 2 Features of 80C51GB.. microcontroller 42

2.1 Features 42

2.2 I/O ports P0-P5 43

2.2.1 Operation of I/O ports. 43

2.2.2 Writing to port.. 46

2.3 Features of the 8XC51GB.. interrupt system 49

Enable/disable interrupts. 50

Interrupt priority management. 51

external interrupts. 54

2.3. ADC node 56

2.4. Hardware watchdog 61

2.5. Clock Failure Detection 63

2.6. Matrix of programmable counters RSA 64

2.6.1. Structure PCA.. 64

2.6.2. PCA Counter Mode Register (CMOD) 66

2.6.3. PCA counter control register (CON) 67

2.6.4. Compare/fix modules. 68

2.7. Enhanced Serial Port 76

2.8. Timers/Counters 79

Pin assignment of 8XC51GB.. group microcontrollers 86

Chapter 3 Programming MK 8051GB.. 89

3.1. Software model 89

3.2 Data types 93

3.3 Ways of addressing data 93

3.4 Command system 95

3.4.1 General characteristics. 95

3.4.2 Command types. 96

3.4.3 Types of operands. 97

3.4.4 Microcontroller data transfer commands. 98

3.4.5 Arithmetic instructions 8051.101

3.4.6 8051 MCU Logic Commands. 104

3.4.7 8051 Bit Operation Commands. 106

3.5 Debugging programs 111

Chapter 4. ASM-51 Programming Language. 112

4.2 Writing program text 113

4.3 Language alphabet. 114

4.4 Identifiers. 115

4.5 Numbers 117

4.6 Directives 118

4.7 Implementation of subroutines in ASM51 122

4.7.1 The structure of the subroutine-procedure in the ASM51 language. 122

4.7.2 Passing parameter variables to a subroutine. 123

4.7.3 Implementation of subprograms-functions in the ASM51 language. 123

4.7.4 Implementation of interrupt handling routines in the ASM51 language. 124

4.8 Structured programming in assembly language. 125

4.9 Peculiarities of translation of multi-module programs.. 126

4.10 Using segments 128

4.10.1 Partitioning the MK memory into segments .. 128

4.10.2 Absolute memory segments. 129

4.10.2 Relocatable memory segments. 131

Chapter 5. The C-51 Programming Language. 134

5.1 General characteristics of the language 134

5.3 Structure of C-51 programs 136

5.3. Elements of the C-51 programming language 138

5.3.1. Symbols.. 138

5.3.2. Lexical units, separators and the use of spaces. 141

5.3.3 Identifiers.. 142

5.3.4 Keywords. 143

5.3.5 Constants.. 143

5.4. Expressions in language statements 146

programming C-51 146

5.5. Operation Priorities 148

5.6. C-51 programming language statements 149

5.6.1. declaration operators. 150

5.6.2 Executable statements.. 150

5.6.3 Assignment operator. 151

5.6.4 Conditional statement. 151

5.6.5 Structural operator (). 152

5.6.6 The for loop statement. 152

5.6.7 Loop statement with condition check up to the while loop body. 153

5.6.8 Loop statement with condition check after loop body do while. 154

5.6.9 The break statement. 155

5.6.10 The continue statement. 155

5.6.11 Switch selection statement. 155

5.6.12 The goto operator. 157

5.6.13 Operator expression. 158

5.6.14 Return statement from subroutine return. 158

5.6.15 Empty statement. 158

5.7. Declaring Variables in the C-51 Programming Language. 159

5.7.1. Variable declaration. 159

5.7.3 Integer data types. 161

5.7.4 Floating point numbers. 162

5.7.5 Variables of enumerated type. 162

5.7.6. Declaring arrays in the C-51 programming language. 164

5.7.7. Structures.. 165

5.7.8. Associations (mixtures) 166

5.8. Using Pointers in C-51 167

5.8.1. Declaring pointers. 167

5.8.2. Untyped pointers. 168

5.8.3. Memory dependent pointers. 169

5.9. Declaring new types of variables 169

5.10. Data initialization 170

5.11. Using subroutines in the C-51 programming language. 170

5.11.1. Definition of subroutines.. 171

5.11.2. Subprogram parameters .. 173

5.11.3. Advance declaration of subroutines.. 174

5.11.4 Calling subroutines.. 176

5.11.5 Recursive subprogram call.. 176

5.11.6 Interrupt routines. 177

5.11.7 Scope of Variables and Subroutines.. 178

5.12. Multi-module programs 179

Chapter 6. Preparing Programs in the Keil μVision2 Integrated Development Environment. 182

6.1 Creating an ASM-51 project 182

6.2 Example of creating a C project for a training controller in the Keil μVision2 IDE 188

Chapter 7 Learning Controller Description .. 199

7.1. Controller structure 199

7.2. Address space 200

7.2.1. Memory allocation. 200

7.2.2 External memory. 201

7.2.3. Internal data memory. 202

7.3. I/O port allocation 202

7.4. Serial port………………………………...203

7.5. Working with LCD 205

7.6. Controller panels…………………………………………………213

APPENDIX P2 STRUCTURE OF THE REPORT ON LABORATORY WORK……..217

Appendix P3 Codes of machine commands. 217

References... 224

Introduction

In the development of specialties related to the automation of technological processes and production, the study of microcontrollers is one of the important sections.

There is a continuous development and emergence of more and more 16- and 32-bit microcontrollers and microprocessors in the world, but the largest share of the world microprocessor market still remains with 8-bit devices. According to all forecasts of analytical companies for the near future, the leading position of 8-bit microcontrollers in the world market will continue.

Currently, among all 8-bit microcontrollers, the MCS-51 family is the undisputed leader in the number of varieties and the number of companies producing its modifications. It takes its name from the first representative of this family - the microcontroller 8051. A successful set of peripherals, the possibility of a flexible choice of external or internal program memory and an affordable price ensured this microcontroller was a success in the market.

Advantages of the MCS-51 family:

architecture, which is the de facto standard;

The extreme breadth of the family and the variety of opportunities;

Availability of high-performance and extended versions of processors;

a significant number of freely available software and hardware developments;

ease of hardware programming, including in-circuit programming;

low cost and availability of basic chips;

Availability of specialized versions of controllers for special conditions of use

Availability of versions of controllers with a reduced level of electromagnetic interference;

· wide popularity among the developers of the older generation, both in the world and in the CIS countries;

Support of architecture by leading educational institutions of the world.

And, finally, the main advantage: having mastered the basic chip of the family, it is easy to start working with such computing "monsters" as Cygnal, Dallas Semiconductor, Analog Devices, Texas Instruments microcontrollers.

The MCS-51 family includes a whole range of microcircuits from the simplest microcontrollers to quite complex ones. To date, there are more than 200 modifications of microcontrollers of the 8051 family, produced by almost 20 companies. Every year there are more and more variants of representatives of this family.

The main areas of development are:

increase in speed (increasing the clock frequency and redesigning the architecture);

reduction of supply voltage and power consumption;

· increase in the amount of RAM and FLASH memory on a chip with the possibility of in-circuit programming;

· introduction of complex devices such as drive control systems, CAN and USB interfaces, etc. into the microcontroller periphery.

Microcontrollers of the MCS-51 family allow you to perform both the tasks of controlling various devices and implementing individual nodes of the analog circuit. All microcircuits of this family work with the same command system. Most of them are carried out in the same cases with the same pinout (numbering of the legs for the case). This makes it possible to use microcircuits of different manufacturers for the developed device without altering the circuit diagram of the device and the program.

The main manufacturers of varieties of the 51st family in the world are Philips, Siemens, Intel, Atmel, Dallas, Temic, Oki, AMD, MHS, Gold Star, Winbond, Silicon Systems and a number of others.

Characteristics of analogues of microcontrollers of the MCS-51 family (Intel 8XC51FA, 8XC51GB, 80C152) with advanced features are given in Table. IN 1.

Table B.1

	RAM	ROM	SAR	ADC	WDT	T/C	Afterbirth. Channels	Peculiarities
Atmel: AT89C2051
	-	-	-	-		UART	Flash 2 Kb
AT89C4051		-	-	-	-		UART	Flash 4 Kb
AT89S4D12		128K	-	-	-		UART, SPI	Flash 4 Kb
DALLAS Semiconductor: DS5000FP
	-	-	-	+		UART	bootstrap loader
DS5001FP		-	-	-	+		UART	bootstrap loader
DS8xC520		16K	-	-	+		2xUART	2DPTR
SIEMENS: C505C
	16K	-	+	+		UART, CAN	8DPTR
C515C		64K	-	+	+		UART+SSC+CAN	4 PWM, 8 DPTR
Philips: *89C51RA+
	-	+	-	+		UART	2 DPTR, lvl 4 interrupt, clock out, Flash 8K
P51XAG1x		8K	-	-	+		2 UARTs
Intel: 8xC51RA
	8K	-	+	+		UART	4 levels IRQ, clock out
8XC196KC	64K	16K	-	+	-		UART	3 PWM
80C196KB	64K	8K	-	+	-		UART	PWM

Chapter 1 MCS51 Family Architecture

8-bit single-chip microcontrollers of the MCS-51 family have gained great popularity among developers of microprocessor control systems due to their well-designed architecture. The microcontroller architecture is a set of internal and external software-accessible hardware resources and a system of commands. The architecture of the MCS-51 family is largely determined by its purpose - the construction of compact and low-cost digital devices. Microcontrollers that perform all the functions of a microcomputer using a single microcircuit are called single-chip computers (OEVMs).

Intel has released about 50 models based on the operating core of the Intel 8051 microcontroller. At the same time, many other companies, such as Atmel, Philips, began production of their microcontrollers developed in the MCS-51 standard.

General characteristics

The main characteristics of the family:

· 8-bit central processing unit (CPU), focused on the control of executive devices;

· The CPU has a built-in circuit of 8-bit hardware multiplication and division of numbers;

The presence in the instruction set of a large number of operations for working with directly addressable bits makes it possible to talk about a processor for working with bit data (Boolean processor);

internal (on-chip) program memory of a mask or reprogrammable type, which has a volume of 4 to 32 Kb for various crystals, it is absent in some versions;

· at least 128 bytes of data resident RAM, which is used for organization, register banks, stack, and user data storage;

· at least 32 bidirectional interface lines (ports), individually configured for input or output of information;

· two 16-bit multi-mode counters/timers used to count external events, organize time delays and clock the communication port;

· Bidirectional duplex asynchronous transceiver (UART) designed to organize communication channels between the microcontroller and external devices with a wide range of information transfer rates. There are means for hardware-software integration of microcontrollers into a connected system;

· a two-level priority interrupt system that supports at least 5 interrupt vectors from 4 internal and 2 external event sources;

built-in clock generator.

Structural scheme

The block diagram of the controller is shown in Figure 1.1 and consists of the following main functional units: a control unit, an arithmetic logic unit, a timer/counter unit, a serial interface and interrupt unit, a program counter, data memory, and program memory. Bilateral exchange is carried out using an internal 8-bit data highway. Almost all representatives of the MCS-51 family are built according to this scheme. Various microcircuits of this family differ only in special-purpose registers (including the number of ports).

Control and synchronization unit (Timing and Control)- designed to generate synchronizing and control signals that ensure the coordination of the joint operation of the OEVM units in all permissible modes of its operation. The control unit includes:

device for forming time intervals;

input-output logic;

instruction register;

electricity consumption management register;

command decoder, computer control logic.

Rice. 1.1. Structural diagram of the I8051 controller.

Time slotting device is intended for generation and output of internal synchronization signals of phases, cycles and cycles. The number of machine cycles determines the duration of instruction execution. Almost all OEVM commands are executed in one or two machine cycles, except for the multiplication and division instructions, the duration of which is four machine cycles. Let us denote the frequency of the master oscillator through F g. The duration of the machine cycle is 12/F g, or 12 periods of the signal of the master oscillator. The input-output logic is designed to receive and issue signals that ensure the exchange of information with external devices through the input/output ports P0-P3.

Command register is designed to record and store an 8-bit operation code of the command being executed. The operation code, with the help of a command decoder and computer control logic, is converted into a microprogram for command execution.

Demand Control Register (PCON) allows you to stop the operation of the microcontroller to reduce power consumption and reduce the level of interference from the microcontroller. An even greater reduction in power consumption and noise reduction can be achieved by stopping the master oscillator of the microcontroller. This can be achieved by toggling bits in the PCON demand control register. For the nMOS manufacturing option (1816 series or foreign chips that do not have the letter "c" in the middle of the name), the power control register PCON contains only one bit that controls the baud rate of the SMOD serial port, and there are no power consumption control bits.

Arithmetic Logic Unit (ALU) is a parallel eight-bit device that provides arithmetic and logical operations. ALU consists of:

accumulator registers, holding registers TMP1 and TMP2;

ROM constants;

adder;

additional register (register B);

battery (ACC);

program status register (PSW).

Register accumulator and holding registers- eight-bit registers designed to receive and store operands for the duration of operations on them. These registers are not programmatically accessible.

ROM constants ensures the development of a correcting code for binary-decimal data representation, a mask code for bit operations, and a constant code.

Parallel 8-bit adder is a combination-type circuit with sequential transfer, designed to perform arithmetic operations of addition, subtraction and logical operations of addition, multiplication, inequivalence and identity.

Register B- an eight-bit register used during multiplication and division operations. For other instructions, it can be considered as an additional scratchpad register.

Battery- an eight-bit register designed to receive and store the result obtained when performing arithmetic-logical operations or shift operations

Serial Interface and Interrupt Block (SIP) designed to organize the input - output of sequential information flows and the organization of the program interrupt system. The block includes:

buffer PIP;

control logic;

control register;

transmitter buffer;

receiver buffer;

serial port transceiver;

interrupt priority register;

interrupt enable register;

interrupt flag processing logic and vector generation scheme.

Program Counter is designed to form the current 16-bit address of the internal program memory and the 8/16-bit address of the external program memory. The program counter consists of a 16-bit PC buffer, a PC register, and an increment circuit (incrementing content by 1).

Data memory (RAM) is intended for temporary storage of information used during the execution of the program.

Ports P0, P1, P2, P3 are quasi-bidirectional input-output ports and are designed to ensure the exchange of information between the OEVM and external devices, forming 32 input-output lines.

Program Status Register (PSW) is designed to store information about the state of the ALU during the execution of the program.

Program memory (EPROM) designed to store programs and is a read-only memory (ROM). Various microcircuits use masked, UV-erasable or FLASH ROMs.

Data Pointer Register (DPTR) designed to store a 16 - bit address of external data memory.

Stack pointer (SP) is an eight-bit register designed to organize a special data memory area (stack), in which you can temporarily store any memory cell.

1.3 8051 microcontroller pin assignment(Fig. 1.2)

· U ss - the potential of the common wire ("earth");

U cc - main supply voltage +5 V;

· X1,X2 - conclusions for connection of a quartz resonator;

· RST - input of the general reset of the microcontroller;

PSEN - external program memory permission, issued only when accessing external ROM;

· ALE - external memory address strobe;

· EA - disable internal program memory; level 0 at this input causes the microcontroller to execute the program only from the external ROM; ignoring the inner (if the latter exists);

Rice. 1.2. Pin assignment 8051.

P1 - eight-bit quasi-bidirectional input/output port, each bit of the port can be programmed both for input and output of information, regardless of the status of other bits;

· P2 - an eight-bit quasi-bidirectional port, similar to P1, the pins of this port are used to issue address information when accessing external program or data memory (if 16-bit addressing of the latter is used). In addition, port pins are used when programming to enter the high-order bits of the address into the microcontroller;

· РЗ - an eight-bit quasi-bidirectional port, similar to Р1, the pins of this port can perform a number of alternative functions that are used in the operation of timers, a serial I / O port, an interrupt controller, and external program and data memory;

· P0 - multiplexed eight-bit bidirectional port of input-output of information, through this port at different points in time the low byte of the address and data are output.

Memory organization

The entire MCS-51 series has a Harvard architecture, i.e. separate program and data memory address spaces. The memory structure is shown in fig. 1.3.

The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on a chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base chip), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to internal or external ROM is determined by the value of the signal at the EA (External Access) pin:

EA=V cc (supply voltage) - access to internal ROM;

EA=V ss (ground potential) - access to external ROM.

For ROMless chips, the EA pin must be permanently connected to V ss .

Rice. 1.3. Memory organization of the MCS-51 family

External ROM read strobe - (Program Store Enable) is generated when accessing external program memory and is inactive during access to the ROM located on the chip. The low program memory address area is used by the interrupt system. The 8051 base chip architecture supports five interrupt sources:

two external interrupts;

two interrupts from timers;

interrupts from the serial port.

On fig. 1.4 shows a map of the lower area of ​​program memory.

Rice. 1.4. Map of the lower area of ​​program memory

Program memory (ROM)

For microcontrollers of the 8051 family, program memory and data memory are independent and independent devices, addressed by various commands and control signals.

The amount of built-in program memory located on the 8051 microcontroller chip is 4 KB (in the family up to 32). When accessing external program memory, all 8051 microcontrollers always use a 16-bit address, which provides them with access to 64 KB of ROM. The microcontroller accesses program memory when reading the opcode and operands (using the PC program counter), as well as when executing commands to copy a byte from program memory to the accumulator. When executing data copy commands, the addressing of the program memory cell from which data will be read can be carried out using both the PC counter and a special two-byte data pointer register DPTR.

Data memory (RAM)

The amount of on-chip data memory is 128 bytes. The external data memory can be up to 64 KB. The first 32 bytes are organized into four banks of general purpose registers, designated respectively bank 0 - bank 3. Each of them consists of eight registers R0-R7. At any time, the program is available, with register addressing, only one bank of registers, the number of which is contained in the third and fourth bits of the PSW program status word.

8051 Microcontroller Bit Area Addresses

Table 1.1

Byte address (Hex)	Bit addresses by bit
D7	D6	D5	D4	D3	D2	D1	D0
2F	7F	7E	7D	7C	7B	7A
2E
2D	6F	6E	6D	6C	6B	6A
2C
2B	5F	5E	5D	5C	5B	5A
2A
	4F	4E	4D	4C	4B	4A
	3F	3E	3D	3C	3B	3A
	2F	2E	2D	2C	2B	2A
	1F	1E	1D	1C	1B	1A
	0F	0E	0D	0C	0B	0A
20h

The remaining address space can be configured by the developer at his own discretion: it can accommodate the stack, system and user data areas. Data memory cells can be accessed in two ways. The first way is direct addressing of a memory cell. In this case, the cell address is the operand of the corresponding instruction. The second method is indirect addressing using pointer registers R0 or R1: before executing the corresponding command, one of them must contain the address of the cell to which it is necessary to access.

To access external data memory, only indirect addressing is used using registers R0 and R1 or using the 16-bit pointer register DPTR.

Part of the data memory is a bit area, it has the ability to use special bit commands to address each digit of the memory cells. The address of directly addressable bits can also be written in the form (ByteAddress).(Bit). The correspondence between these two addressing methods can be determined from Table. 1.1.

Ministry of General and Vocational Education of the Russian Federation Novosibirsk State Technical University V.N. Veprik, V.A. Afanasiev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O.V. Malyavko MICROCONTROLLERS OF THE MCS-51 FAMILY Textbook on the courses "Microprocessor systems" and "Design of microprocessor systems" for senior students of the Faculty of Automation and Computer Engineering of all forms of education Novosibirsk 1997 V.N. Veprik, V.A. Afanasiev, A.I. Druzhinin, A.A. Zemskov, A.R. Isaev, O.V. Malyavko. Microcontrollers of the MCS-51 family: Tutorial. - Novosibirsk. The textbook brought to your attention contains a general description of the architecture, functionality and command system of the family of single-chip microcontrollers (Embedded Microcontrollers) MCS-51, manufactured by INTEL. The second part of the manual describes the educational microprocessor controller UMPC-51, offered to students as an object of study when performing a cycle of laboratory work. The material of the manual can be used in course and diploma design, and can also be useful for circuit engineers involved in the development and operation of electronic equipment. The authors express their deep gratitude to CJSC "New Technologies", the official distributor of INTEL, for providing the materials on the basis of which this work was performed. Table 15, ill. 25, list of lit. 12 titles Reviewers: E.D. Baran, G.G. Matushkin. The work was prepared at the Department of Computer Engineering Novosibirsk State © Technical University 2 INTRODUCTION. The family of 8-bit single-chip microcontrollers MCS-51 appeared on the world market in the early eighties. The first modifications of crystals (about 7) were made using high-quality n-MOS (HMOS) technology and were functionally completed single-chip microcomputers of the Harvard architecture, one of the main principles of which is the logical separation of program and data memory address spaces. With the development of semiconductor technology, subsequent versions of the MCS-51 microcircuits began to be manufactured using a more advanced and low-power CMOS (CHMOS) technology (in active mode, the consumption of crystals was increased to 1050 mA). The MCS-51 command system, focused on the implementation of various digital control algorithms, while maintaining some external similarity with the command system of the previous MCS-48 family, has qualitatively expanded, fundamental innovations have appeared in it: bit-oriented operations and bit fields addressed in the data memory, which made it possible to talk about the implementation of a bit processor on a chip; implemented execution of multiplication, division and subtraction commands; improved work with the stack; the group of control transfer commands has been expanded; The command system began to look more symmetrical, that is, less dependent on data transfers through the battery. The functionality of the built-in peripherals has also been expanded with the introduction of: two 16-bit timer-counters; hardware serial duplex port; two-level interrupt system; four 8-bit I/O ports. Fundamental changes in the structure of the time cycle of the processor have led to faster work with external program and data memory, as well as responses to external and internal interrupts. The total size of the address space of the external program and data memory has increased to 128 KB. The 16-bit registers of the program counter (Program Counter) and data pointer (Data Pointer) made it possible to directly access the entire range of addresses, which gave developers the opportunity to implement algorithms for fast processing of large data arrays. All software-accessible nodes of the microcontroller were reduced to a special data memory area (Special Function Register), which made it possible to access them in almost the same way as ordinary cells of resident RAM. In later modifications of crystals, the improvement went along the path of increasing additional functionality while maintaining full software compatibility with earlier versions. Features of the latest modifications of microcontrollers of the MCS-51 family are: completely static design; 3- and 5-volt versions of crystals; a wide range of built-in peripherals; maximum clock frequency - 24 MHz; for individual groups of crystals - 33 MHz. Currently, the MCS-51 includes about 60 versions of crystals, in addition, detailed proprietary documentation is available and available (unfortunately, it has not been translated into Russian yet). To prepare the software for MCS-51 microcontrollers, mainly the ASM-51, C languages ​​are used, for which there are a number of fairly well-proven compilers, libraries of standard subroutines and software emulators produced by various foreign and domestic companies. 3 Despite the sufficient "antiquity" of the family (more than 15 years) and the appearance on the world market in recent years of single-chip microcontrollers of higher performance and improved architecture - MCS-51, MCS-251, MCS-96, MCS-51 controllers will be widely used for a long time. be used in relatively simple embedded control systems. 4 1. INTEL COMPONENT DESIGNATION SYSTEM AND FUNCTIONAL COMPOSITION OF THE MCS-51 FAMILY To label microchips, INTEL uses a notation system consisting of several fields: , automotive version for an extended temperature range (-40 / +125 C) M (Military), version according to military standards (-55 / +125 C) Q or C (Commercial), "commercial" temperature range (0 / +70 C ) with (160 8) - hourly dynamic thermal training; L or E (Extended), "extended" temperature range (-40/+85 C) with (160 8) hour dynamic thermal training; T (Extended), "extended" temperature range (-40/+85 C) without thermal training; I (Industrial), execution according to industrial standards. The second field contains a one- or two-letter prefix indicating the package type of the microcircuit (Package Type). Today there are several dozens of different types of microcircuit packages, therefore, as an example, we will give only some designations: A Ceramic Pin Grid Array, (PGA); C Ceramic Dual In-Line Package, (CDIP); K Ceramic Quad Flatpack Package, (QFP); KD Plastic Quad Flatpack Package, Fine Pitch, Die Down, (PQFP); KU Plastic Quad Flatpack Package, Fine Pitch, Die Up, (PQFP); N Plastic Leaded Chip Carrier, (PLCC); P Plastic Dual In-Line Package, (PDIP); SM Single In-Line Leadless Memory Module, (SIMM); U Plastic Dual In-Line Package, Shrink Dip, (PDIPS); Z Zigzag In-Line Package, (ZIP). The third field can contain up to 15 numeric and alphabetic characters indicating the type of specific device located on the chip. The fourth field can include up to six numeric and alphabetic characters, reflecting various features and versions of microcircuits. Additional information on the types of cases and their design can be found in the book: Packaging Order Number 240800. With regard to the described microcontrollers of the MCS-51 family, the first character of the third field is traditionally (for Intel) equal to "8". The second character of the third field usually indicates the type of built-in ROM: 0 program mask ROM; non-ROM crystal (for later versions of crystals); 1 mask ROM programs (Standard ROM Code, Firmware); 3 mask ROM (for later versions of crystals), (Customizable ROM Code); 7 UFPROM or one-time programmable ROM (EPROM or OTP ROM); 8 EEPROM (Flash - memory on a chip) Next, a letter may follow, indicating the technological features of manufacturing: no letter HMOS technology, 5V power supply; With CHMOS technology, 5V power supply; l CHMOS technology, 3V power supply; 5 The next characters of the third field for microcontrollers of the MCS-51 family are numbers (for example, 31,32,51,54,58,152) and from one to four letters that reflect the functional features of the chips (for example, ROM size, the specifics of a group of chips, the presence of a system protection of program memory from unauthorized access, the possibility of using a more advanced programming algorithm "Quick Pulse" and the like). In the original technical documentation from Intel, all microcontrollers of the MCS-51 family are grouped into groups ("Product Line"), each of which combines the closest versions of crystals in terms of their functionality and electrical parameters. Since the names of microcircuits of one group differ slightly, then to designate each individual group, a generalized symbolism is used, formed from the marking of specific microcircuits, by replacing the differing characters with "X". Thus, the following groups of microcontrollers can be distinguished. 1. Group 8X5X (8051 Product Line and 8052 Product Line): 8031AN, 8051AN, 8751H, 8051AHP, 8751H-8, 8751VN, 8032AN, 8052AN, 8752VN. 2. Group 8ХС51 (80С51 Product Line): 80С31ВН, 80С51ВН, 87С51. 3. Group 8ХС5Х (8ХС52/54/58 Product Line): 80С32, 80С52, 87С52, 80С54, 87С54, 80С58, 87С58. 4. Group 8XC51FX (8XC51FA/FB/FC Product Line): 80C51FA, 83C51FA, 87C51FA, 83C51FB, 87C51FB, 83C51FC, 87C51FC. 5. Group 8XL5X (8XL52/54/58 Product Line): 80L52, 87L52, 80L54, 87L54, 80L58, 87L58. 6. Group 8XL51FX (8XL51FA/FB/FC Product Line): 80L51FA, 83L51FA, 87L51FA, 83L51FB, 87L51FB, 83L51FC, 87L51FC. 7. Group 8XC51RX (8XC51RA/RB/RC Product Line): 80C51RA, 83C51RA, 87C51RA, 83C51RB, 87C51RB, 83C51RC, 87C51RC. 8. Group 8XC51GB (8XC51GX Product Line): 80C51GB, 83C51GB, 87C51GB. 9. Group 8XC152JX (8XC152 Product Line): 80C152JA, 83C152JA, 80C152JB, 80C152JC, 83C152JC, 80C152JD. 10. Group 8XC51SL (8XC51SL Product Line): 80C51SL-BG, 81C51SL-BG, 83C51SL-BG, 80C51-AH, 81C51SL-AH, 83C51SL-AH, 87C51SL-AH, 80C51SL-AL, 81C51SL-AL, 83C51SL-AL, 87C51SL-AL. The first group of microcontrollers includes the younger models of the family, made using n-MOS technology and not recommended for use in new developments, all other groups are made using modern CMOS technology. Microcircuits of the second, third and fourth groups are today the classic representatives of the MCS-51 family. The fifth and sixth groups include 3-volt versions of crystals (Low-Voltage). Crystals of the seventh group are equipped with expanded RAM (Expanded RAM), the volume of which is 512 bytes. Microcircuits of the eighth, ninth and tenth groups are microcontrollers specialized in application (Application Specific). Many of today's applications require high-performance control microcontrollers that use advanced addressing, register architecture, large internal RAM and stack space, and efficiently support high-level language programming. These microcontrollers include New Architecture microcontrollers of the MCS-5 and MCS-251 families, which Intel launched in 1995. The functional composition and key features of the MCS-51/MCS-251 microcontroller are given in the appendix. 6 2. MAIN CHARACTERISTICS OF THE BASIC MODEL OF THE MCS-51 MICROCONTROLLER FAMILY. The basic model of the MCS-51 family of microcontrollers and the basis for all subsequent modifications is the I-8051 microcontroller. Its main features are as follows: eight-bit CPU optimized for control functions; built-in clock generator; program memory address space - 64 K; data memory address space - 64 K; internal program memory - 4 K; internal data memory - 128 bytes; additional features for performing Boolean algebra operations (bitwise operations); 32 bidirectional and individually addressable I/O lines; 2 x 16-bit multi-function timers/counters; full duplex asynchronous transceiver; vector interrupt system with two priority levels and six event sources. The block diagram of the I-8051 is shown in Fig. 1, the pin assignment of the microcircuit is shown in Fig. 2. External interrupts Interrupts 128 bytes T/C 0 counter 4K ROM control RAM T/C 1 inputs CPU BUS 4 I/O Serial OSC control Ports Port P0 P1 P2 P3 T D R D Address/Data Figure 1. Block diagram of the I-8051 The entire MCS-51 series has a Harvard architecture, that is, separate program and data memory address spaces. The organization of memory is shown in Figure 3. The amount of internal (resident) program memory (ROM, EPROM or OTP ROM) located on a chip, depending on the type of microcircuit, can be 0 (ROMless), 4K (base chip), 8K, 16K or 32K. If necessary, the user can expand the program memory by installing an external ROM. Access to the internal or external ROM is determined by the value of the signal at the EA (External Access) pin: EA=Vcc (supply voltage) - access to the internal ROM; EA=Vss (ground potential) - access to external ROM. For ROMless chips, the EA pin must be permanently connected to Vss. The external ROM read strobe - PS EN (Program Store Enable) is generated when accessing external program memory and is inactive during access to the ROM located on the chip. 7 The low program memory area is used by the interrupt system, the 8051 chip architecture provides support for five interrupt sources: two external interrupts; two interrupts from timers; interrupts from the serial port. P1.0 1 40 Vcc P1.1 2 39 P0. 0 (AD0) P1.2 3 38 P0.1 (AD1) P1.3 4 37 P0.2 (AD2) P1.4 5 36 P0.3 (AD3) P1.5 6 35 P0.4 (AD4) P1. 6 7 34 P0.5 (AD5) P1.7 8 33 P0.6 (AD6) RESET 9 32 P0.7 (AD7) (RD) P3.0 10 31 EA/Vpp (TD) P3.1 11 30 ALE/ PROG (INT0) P3.2 12 29 PSEN (INT1) P3.3 13 28 P2.7 (A15) (T0) P3.4 14 27 P2.6 (A14) (T1) P3.5 15 26 P2.5 ( A13) (WR) P3.6 16 25 P2.4 (A12) (RD) P3.7 17 24 P2.3 (A11) XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) Vss 20 21 P2.0 (A8) Fig.2. Pin assignment I-8051 Program memory (Read) Data memory (Read/Write) FFFFH External ROM FFFFH External @DPTR RD memory PSEN WR data @PC MOVC EA=0 Internal memory @DPTR data @PC External Internal FFH upper 128 SFR MOVX ROM ROM 80H EA=0 0000H EA=1 lower 128 00H 0000H PSEN Fig.3. Memory organization of the MCS-51 family 8 Figure 4 shows a map of the lower area of ​​the program memory. ROM Program memory 0033H 002BH Serial Port 0023H Vectors Timer1 001BH interrupts EINT1 0013H Timer0 000BH EINT0 0003H Start address 0000H (Reset) Fig.4. Program memory Interrupt vector addresses are located at intervals of 8 bytes: - 0003H external interrupt 0 (External Interrupt 0) - output IN T 0 ; - 000BH interrupt from timer 0 (by timer overflow flag - T F 0); - 0013H external interrupt 1 (External Interrupt 1) - output IN T 1; - 001BH interrupt from timer 1 (by timer overflow flag - T F 1); - 0023H serial port interrupt (Serial Interrupt = Receive Interrupt or Transmit Interrupt); etc. The data memory is separate from the program memory. In this area, 64K external RAM can be addressed. When accessing the external data memory, the microcontroller CPU generates the corresponding read (RD) or write (W R) signals, interaction with the internal data memory is carried out at the command level, while the RD and W R signals are not generated. External program memory and external data memory can be combined by combining the R D and PS EN signals in a logical AND fashion to produce an external memory (program/data) strobe. The lower 128 bytes of internal data memory (lower 128) are present on all MCS-51 chips and are shown in Figure 5. The first 32 bytes are 4 banks (Register Bank) of 8 registers (R7...R0). Registers R0 and R1 in either bank can be used as indirect address registers. The 16 bytes following the register banks form a block of bit-addressable space. The MCS-51 instruction set contains a wide variety of bit operations, and the 128 bits in this block are directly addressable and addresses range from 00H to 7FH. All bytes in the lower 128-byte half of memory can be addressed either directly or indirectly. The upper 128-byte half of the RAM memory (upper 128) is not present in the I-8051 chip, but is available in the 256-byte RAM versions of the chips. In this case, the "Upper 128" area is only available with indirect addressing. The SFR (Special Function Register) area is only available with direct addressing. The placement of special function registers in the SFR space is shown in Fig.6. They include port registers, timers, peripheral controls, and so on. 9 7FH Pull-time-addressable area 30H (Direct, Indirect) 2FH 7FH 7EH 7DH 7CH 7BH 7AH 79H 78H 2EH 77H 76H 75H 74H 73H 72H 71H 74H 73H 71H 71H 77H 71H 71H 71H 71H 0FH 0FH 0H 0DH 0CH 0FH 0AH 09H 08H 20H 07H 06H 05H 04H 03H 02H 01H 00H 1FH RB3 18H 17H RB2 10H 0FH RB1 08H 07H SP after RESET 00H RB0(R7+R0) Fig.5. Bottom 128 bytes of internal RAM. bit addressing 8 bytes F8H FFH F0H B F7H E8H EFH E0H ACC E7H D8H DFH D0H PSW D7H C8H CFH C0H C7H B8H IP BFH B0H P3 B7H A8H IE AFH A0H P2 A7H 98H SCON SBUF 9FH 90H P1 97H 8FH TH TL1 TL0 80H P0 SP DPL DPH PCO 87H N 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F Fig.6. Placement of special function registers in SFR space. For 16 addresses in the SFR space, both byte and bit addressing is possible. For bit-addressable registers, the hexadecimal address ends with "0H" or "8H". Bit addresses in this area have values ​​from 80H to FFH. The entire series of crystals of the MCS-51 family has a basic SFR set, as in the I-8051 chip, located at the same addresses. However, in crystals, which represent a further development of the family in the SFR region, new registers are added to expand 10